npsm 새물리 New Physics : Sae Mulli

pISSN 0374-4914 eISSN 2289-0041


Research Paper

New Phys.: Sae Mulli 2024; 74: 8-16

Published online January 31, 2024

Copyright © New Physics: Sae Mulli.

Improving the Electrical Performance of Large-area Graphene Transistors Through Vacuum-assisted Annealing

Hyunkyung Lee1, Hyeonseop Lee1, Daehyeon Kim1, Jinho Jeon1, Choongyu Hwang1, Sungkyun Park1,2, Jong Mok Ok1, Kanghyun Kim3, Songkil Kim4, Haeyong Kang1,2*

1Department of Physics, Pusan National University, Busan 46241, Korea
2Research Center for Dielectric and Advanced Matter Physics, Pusan National University, Busan 46241, Korea
3Samsung Display, Yongin 17133, Korea
4School of Mechanical Engineering, Pusan National University, Busan 46241, Korea

Correspondence to:*

Received: October 20, 2023; Accepted: October 30, 2023

This is an Open Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License( which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

To fabricate large-area graphene transistors, the transfer of chemical vapor-deposited graphene onto preferred substrates and the patterning of drain/source electrodes are necessary. However, these transfer and deposition processes commonly employ polymers such as poly(methyl methacrylate) and photoresists, which can leave residual polymers and adsorbed molecules on the channel, thus affecting the electrical properties of the devices. In this study, we investigated the effects of heat treatment on the device characteristics related to the polymer residues and adsorbates on graphene surface by analyzing the transfer curves. Our findings demonstrate that proper vacuum annealing can enhance the device’s performance and reduce contact resistance. Moreover, we propose an advanced procedure that incorporates thermal annealing under vacuum after each step of polymer removal. This method is particularly beneficial for enhancing the contact and surface properties of channels in general fabrication processes involving polymers.

Keywords: Surface adsorbates, Graphene field-effect transistors, Vacuum-assisted thermal annealing, Laminating transfer

For the industrial applications of two-dimensional (2D) materials, efforts for their large-scale growth, particularly through chemical vapor deposition (CVD), are underway[1-7

]. In addition, numerous attempts have been made to utilize 2D materials for various devices. However, for this, transferring these materials onto diverse substrates is essential[8-12]. For instance, for graphene grown on a Cu foil, the commonly employed transfer method involves chemical etching using a Cu etchant, which requires the use of an assist thin-film layer, such as poly(methyl methacrylate) (PMMA), to separate the monolayer graphene from the Cu foil[13-16]. Another approach is to physically remove graphene from Cu foils using thermal-release tapes or hot rolls[17-21]. In case of a hot rolling process, it is possible to achieve a transfer in which graphene is exposed only to water by using a water-soluble polyvinyl alcohol (PVA) film[22, 23].

On the other hand, polymers and solutions are often utilized in electrode patterning for device operation. Electron-beam (e-beam) lithography and photolithography involve coating an e-beam resist and photoresist (PR) on the graphene surface, followed by development after exposure. Consequently, the presence of adsorbates with residual polymers on the graphene surface and at the interface between the graphene and electrode cannot be disregarded[24-27].

Efforts to mitigate the influence of polymer residue generated during the transfer and patterning processes on the electrical characteristics of graphene devices are ongoing. The introduction of high-temperature treatments, which has been employed for residue removal, can inadvertently impair the performance of graphene transistors rather than improving it[28]. To enhance the performance of large-area graphene transistors that require multiple processing steps, the focus should be on improving the electrical characteristics rather than giving priority to polymer removal. In this study, we investigated the characteristics of graphene transistors through various fabrication processes and the effects of thermal annealing on device performance. Additionally, we propose an enhanced device fabrication process that achieves exemplary performance even when using both PMMA and PR.

1. Graphene transfer

We employed two methods to transfer CVD-grown graphene (purchased from UniNanoTech Co., Ltd.) from a Cu foil onto a SiO2/Si substrate as depicted in the transfer methods shown in Fig. 1(a). The first approach is etching a Cu foil in a solution to separate the graphene layer. But before immersing the Cu foil in an etchant, a selective etching process is necessary to eliminate residual graphene from the backside of the Cu foil, which is typically generated during growth. To safeguard the graphene on the front side of the Cu foil, it was spin-coated with 950 PMMA C4 (Kayaku Advanced Materials) at 2000 rpm twice and annealed at 100 °C for 2 min. Subsequently, the PMMA/graphene/Cu foil/graphene was subjected to O2 plasma in a reactive ion etching system, enabling the etching of the backside-graphene layer. Next, the PMMA/graphene/Cu foil was floated on an (NH4)2S2O8 solution, acting as the Cu etchant. The Cu etchant on the PMMA/graphene surface was diluted with deionized (DI) water multiple times, and the PMMA/graphene film was transferred onto a cleaned SiO2/Si substrate. After thorough moisture removal, acetone was used to eliminate the PMMA, resulting in CVD-grown graphene on the desired substrate.

Figure 1. (Color online) Schematics of fabrication processes for CVD-grown graphene field effect transistors. (a) Four different fabrication processes were used to create CVD-grown graphene field-effect transistors, involving a combination of two transfer methods and two patterning methods. Wet etching (E) and laminating (L) were used to transfer CVD-grown graphene from a Cu foil onto the substrate. Two patterning methods were used to form source/drain electrodes using photolithography (P) and a metal mask (M). The EP, LP, EM, and LM devices were fabricated using processes ① (wet etching + photolithography), ② (wet etching + metal mask), ③ (laminating + photolithography), and ④ (laminating + metal mask), respectively. (b) Schematics of laminating methods for transferring CVD-grown graphene are shown (see experimental methods for details).

In the second method, a laminator was utilized for graphene transfer, as depicted in Fig. 1(b). Initially, the Cu foil with CVD-grown graphene was immersed in DI water at room temperature for over 10 days to oxidize the Cu layer, weakening the bond between graphene and the foil. Then, the front surface of the graphene/Cu foil was attached to a PVA film which was pre-washed using IPA. The assembly was passed through a laminator at a speed of 20 cm/min and a temperature of 110 °C. To enhance adhesion between the PVA film and graphene, the graphene/PVA film was subjected to additional heat treatment at 110 °C for 3 min using a hot plate. After mechanically separating the graphene/PVA film from the Cu foil, the film was inverted and affixed to a cleaned SiO2/Si substrate. The film was subsequently passed through a coating machine and annealed under identical conditions. The transfer process concluded with a 24 h immersion of the PVA film in DI water and its subsequent removal, finalizing the process.

2. Patterning and metal deposition

After transferring the CVD-grown graphene onto the SiO2/Si substrate, source/drain electrode patterns were formed using two methods, as indicated in the patterning methods shown in Fig. 1(a): photolithography and metal masks. For photolithography, AZ5214E (Clariant GmbH) served as the PR, and a pattern was created on graphene using an image reversal process (using Labsys LIT-2000 manufactured by Nextron). The deposition of Au/Ti (45 nm/5 nm) on graphene was accomplished via an e-beam evaporator, followed by the dissolution of PR in acetone to complete the lift

Alternatively, a metal mask with an identical pattern to the one employed in photolithography was utilized. The same metals (Au/Ti) were then deposited onto graphene using an e-beam evaporator.

3. Device classification

Figure 1(a) depicts the fabrication process of four distinct device combinations created through two transfer methods (etching transfer, ``E" and laminating transfer, ``L") and two metal-electrode patterning processes (photolithography, ``P" and metal mask, ``M"). The devices are denoted as EP, EM, LP, and LM for classification purposes. As an example, the EP device refers to a field-effect transistor (FET) formed by chemically etching the Cu foil after supporting graphene with a PMMA layer, followed by electrode patterning on the channel using photolithography.

We fabricated multiple devices using the methods illustrated in Fig. 1(a) and recorded the transfer curve of the graphene channel with an SiO2 layer as the gate insulator. The representative results of the devices fabricated by each process are shown in Fig. 2. Our analysis focused on the change in the specific position and shape of graphene conductance curve to evaluate the device characteristics. Intrinsic graphene exhibits a V-shaped conductance pattern, steadily increasing on both sides of the charge neutrality point (CNP), where the conduction and valence bands intersect. Doping graphene with p-type (n-type) dopants causes a shift in the gate voltage corresponding to the CNP (VCNP), aligning with the local minimum of conductance, in a positive (negative) direction. Nonuniform doping effects in the channel or contact region can distort the conductance curve, deviating from its original V-shape[29, 30]. Additionally, the formation of trap states due to defects or impurities introduces hysteresis[31, 32].

Figure 2. (Color online) (a–d) Electrical properties of graphene in various devices. All drain currents were measured with a drain voltage of 1 mV. (a) Transfer curve of the EP device before (violet) and after (magenta) heat treatment. (b) Transfer curve of the EM device before (orange) and after (green) heat treatment. (c) Transfer curve of the LP device before (brown) and after (red) heat treatment. (d) Transfer curve of the LM device before (gray) and after (blue) heat treatment. All solid lines and dashed lines in the transfer curve represent a forward sweep and backward sweep of the gate bias, respectively. (e–h) AFM topography images of graphene sheet on SiO2 substrate treated with various processes. Left and right images show graphene surface before and after annealing at 200 °C for an hour under a low vacuum condition, respectively. All scale bars represent a length of 2 μm.

The EP device was fabricated using PMMA and PR for wet etching transfer and photolithography, respectively, resulting in a heavily p-doped device, where VCNP initially appeared at approximately 40 V, as indicated by the violet line in Fig. 2(a). The p-doping effect could also be observed in the conductance characteristics of the EM device, represented by the orange line in Fig. 2(b), which employed PMMA during the transfer process. It is widely acknowledged that polymer residues on graphene can induce p-doping or degrade electrical properties, such as mobility[27, 33]. To enhance the gate bias response, we conducted a 1 h heat treatment at 200 °C under vacuum conditions[28]. As expected, VCNP shifted negatively to approximately 15 and 5 V after the heat treatment, as demonstrated by the magenta line in Fig. 2(a) and the green line in Fig. 2(b), respectively.

In the EP device, aside from p-doping, another distinctive characteristic is observed. The presence of polymer residues or adsorbed molecules also caused a notable feature of weakly distorted behavior in the transfer curve, deviating from the typical V-shape before heat treatment. This can be confirmed in Fig. 2(c), and both cases, it became more pronounced after annealing. Therefore, considering the commonalities in the shape of graph, in previous studies, this distortion can be attributed to nonuniform doping in the contact region, resulting from metal electrodes, or variations in the vertical electric field due to device geometry, such as a partially covered top-gate electrode[29, 30, 33]. In this study, we investigated the possibility of a local distribution of polymer residues and/or adsorbed molecules inducing local doping effects while excluding the influence of metal electrodes, as all devices employ Au/Ti electrodes. Further details will be covered later with additional experimental results.

Figure 2(d) shows the transfer curve of the device fabricated through the LM process. Initially, the graphene exhibited a V-shaped conductance without distortion in both forward and backward sweeps immediately after fabrication. However, hysteresis was observed, and the difference between the two VCNP values was approximately 15 V, which was not observed in the other three devices. After annealing the device at 200 °C for 1 h under vacuum, the hysteresis disappeared, as shown by the blue line in Fig. 2(d). As LM devices utilize a PVA film and only employ water without any other solutions during fabrication, it can be assumed that water molecules adsorbed onto the graphene surface act as traps, inducing hysteresis, as demonstrated by the gray line in Fig. 2(d)[31, 32]. After thermal annealing under vacuum, we believe that the removal of water molecules is responsible for the excellent performance in the most of LM devices with the VCNP located near 0 V and a clear V-shape, different from those of the other three devices.

By systematically investigating various devices developed via different fabrication processes, we discovered that frequent use of polymers can induce undesirable effects on device characteristics, including doping-induced effects and distorted conductance behavior. Furthermore, it is clear that thermal annealing plays a crucial role in improving device performance, which can be easily found in many references[28, ]. First of all, we checked the effect of vacuum-assisted thermal annealing on the removal of polymer residue. A temperature of 400 °C is recommended to remove polymer completely in the commercial recipe and the vacuum annealing at 200 °C does not completely remove most of polymer residues from the graphene surface as observed in Figs. 2(e)–(h) through atomic force microscopy (AFM). Consequently, the observation of reduced p-doping effect and increased distortion after thermal annealing under vacuum can be interpreted as the reduction of adsorbed molecules present in the channel. The mechanism is not clearly elucidated even though we tried to solve it by X-ray photoelectron spectroscopy or Raman measurement. Nevertheless, since it is evident that vacuum-assisted annealing is very easy and effective method to improve the device characteristics, our primary focus was to efficiently utilize thermal annealing with the aim of optimizing process conditions.

To verify the impact of heat treatment, we conducted an experiment to isolate the doping effect on the graphene channel free from the contact part using LM devices that are considered to have little effect of polymer residues or solutions after the removal of water by post-annealing. Figure 3(a) outlines the process of coating and erasing polymers with acetone from the completed LM device, with transfer curve measurements performed at each step.

Figure 3. (Color online) Electrical properties of adsorbate-free graphene devices during replicating experiments. (a) Schematics of the testing processes to demonstrate the effect of heat treatment. The procedures of coating and erasing the polymers with acetone on the completed LM device and annealing the device are shown. The magenta circles on the channel surface represent adsorbates. (b, c) Transfer curves of the LM device with several steps are shown in Fig. 3(a), and each row includes the following processes: (i) After annealing the LM device at 200 °C for an hour under vacuum. (ii) After coating PR (b), or PMMA (c) with the same treatment as that in Fig. 1(a). (iii) After erasing PR (c), or PMMA (c) using acetone. (iv) After a second annealing under vacuum. All solid lines and dashed lines in the transfer curve represent a forward sweep and backward sweep of the gate bias, respectively.

Initially, the LM device exhibited typical V-shaped characteristics with minimal hysteresis after heat treatment, as depicted in Figs. 3(b)-(i) and 3(c)-(i). However, when PR or PMMA was coated on graphene under the same conditions as in the EP, EM, and LP devices, heavily p-doping effects emerged, clearly shifting VCNP positively, due to fully covered channel with polymers, as seen in Figs. 3(b)-(ii) and 3(c)-(ii). Immediately after erasing the polymers with acetone, we observed a distortion in the V-shape, as shown in Figs. 3(b)-(iii) and 3(c)-(iii). One thing we should mention here is that the extent of polymer removal and conductance distortion may vary across devices. Nevertheless, after vacuum-assisted heat treatment, the distortion vanished (Figs. 3(b)-(iv) and 3(c)-(iv)) in the most of devices, and the initial characteristics before polymer coating were restored, regardless of device’s conductance. In other words, the components that induce partial doping may remain in the use of only a solvent. Moreover, this issue will be more challenging in the contact region after the metals were deposited. The distorted behavior observed in the transfer curve even after post-annealing in Fig. 2 can be attributed to the relatively exacerbated doping in the region covered by the electrode compared to the channel, which cannot be eliminated through vacuum-assisted annealing.

When compared to other devices, it is evident that the LP device exhibits an overall lower conductance, shown as Fig. 2 even though the dimension of channels of the devices were the same. This lower conductance is commonly observed in all LP devices and may result from contact degradation occurring in the contacts or channels when both PVA and PR are used within the same device without any vacuum annealing process. On the other hand, during the vacuum heat treatment of the LM device followed by the PR coating process in Fig. 3(b), there is no observed decrease in conductance. This suggests that the introduction of heat treatment during the process can be a method to prevent performance degradation, such as an increase in contact resistance. Furthermore, through annealing at 200 °C for 1 h under low-vacuum conditions (10-3 Torr), the removal of the cause of doping can be expected to enhance the device’s characteristics. Based on this, we propose an improved process that incorporates thermal annealing after each polymer removal step to enhance device performance in the general process involving two polymers, such as PR and PMMA used in the EP process.

Prior to implementing the new process in EP devices, we firstly determined whether thermal annealing caused any damage to graphene due to the thermal expansion, contraction, or increased presence of adsorbates, as the remaining PR on graphene is exposed to heat. Specifically, we investigated the behavior of PR (AZ5214E), as it experiences a significant weight decrease around 200 °C[37]. To do so, we performed a test on our reusable testing platform to erase the PR exposed to heat during vacuum annealing. Figures 4(a)–(e) demonstrate the conductance behaviors of a LM device during PR coating, annealing, and erasure. The transfer curve remained unchanged after annealing (Fig. 4(c)) compared to that for the PR-coated transistor (Fig. 4(b)). Finally, as depicted in Fig. 4(e), it was confirmed that the PR was highly resistant to 200 °C heat, as evidenced by the recovery of the conductance to its original transfer curve.

Figure 4. (Color online) Electrical properties and schematics for advanced device fabrication process. (a–e) Schematics and transfer curves of the LM device during annealing with PR and erasing: After annealing under vacuum (a), after coating with PR (b), after annealing the PR under vacuum (c), after erasing the PR using acetone (d), and after the third annealing under vacuum (e). (f) Combined fabrication method with EP and annealing processes to remove all polymer residues. After transferring graphene with PMMA as an assist layer, the PMMA is erased using acetone and removed by heat treatment under vacuum. After developing with PR to make source/drain electrodes, the PR residue on the contact part is removed by vacuum annealing. After depositing electrodes and the lift-off process, the residual PR on the graphene channel is removed by final heat treatment. Green and red circles on graphene surface represents adsorbates generated after removal of PMMA and PR, respectively. (g) Transfer curve of the EP device according to the process in (f). (h) Parameters extracted from transfer curves of 16 conventional EP devices and 10 new EP devices after vacuum-assisted annealing. The upper and lower graphs display the distributions of VCNP and hole mobility of channel, respectively.

To address the issue of doping, we devised a new device fabrication process that incorporates vacuum annealing at each step, as shown in Fig. 4(f). Now, we introduced two additional vacuum annealing steps in the fabrication of EP devices as shown in Fig. 4(f): (1) after removing the PMMA layer used for transferring CVD-grown graphene, and (2) after PR development (before metal deposition for electrodes). Final annealing was conducted just before the device measurement. Notably, neither p-doping effect nor distortion in graphene conductance observed in the most devices from the new EP process, as shown in Fig. 4(g). This clearly proves that contact resistance between graphene and electrodes has improved significantly through a second heat treatment. As can be observed in Fig. 4(h), devices fabricated using this novel EP process exhibit a close-to-0 V VCNP compared to conventional EP devices, while also demonstrating an enhancement in mobility. By employing vacuum heat treatment right after every process of erasing the polymer, we successfully fabricated CVD-graphene devices with stable and uniform quality.

We have fabricated and analyzed various devices with different processes and observed that LM devices, laminating transfer and metal mask without using PMMA and PR, exhibited superior device characteristics. By replicating experiments involving polymer coating and erasure on a reusable testing platform, we confirmed that vacuum-assisted heat treatment can effectively clean the graphene surface by reducing doping and distortion behavior. We proposed a novel fabrication method that incorporates thermal annealing under moderate vacuum condition after each polymer erasure step in the standard procedure. This method has the potential to enhance device performance without compromising graphene integrity, owing to the utilization of low vacuum and low temperature.

We acknowledge the support provided by the Basic Science Research Program (NRF-2021R1A2C2013289), a Basic Science Institute (National Research Facilities and Equipment Center) grant funded by the Ministry of Education (No. 2021R1A6C101A429), and the BK21 FOUR Program by the Pusan National University Research Grant, 2021.

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