The so termed “normally-off” mode AlGaN/GaN high-electron-mobility transistors (HEMTs) with threshold voltage of more than 1 V has a great attraction in stable high power switching applications which require limited gate signal noise during on/off modulation[1-6]. Recently, p-(Al,In)GaN layer placed on top of the AlGaN barrier has been introduced to lift the channel potential. Such modification induces the depletion of 2-dimensional electron gas (2DEG) at zero gate bias level, which can be advantageous in obtaining stable and high V_th when the gate is unbiased[7-10]. Such p-gate GaN HEMTs are good structures for a normally-off operation but they suffer from relatively high forward gate current[7, 8]. Furthermore, p-GaN gate HEMT has higher leakage current and lower drain current due to the interface trap states[9-12]. In particular, the so called “dynamic on-resistance (R_ON),” which is known to degrade the current collapse, results in a degradation of output power. Such phenomenon is well explained by the partial depletion of 2DEG due to charged surface states between gate and drain and/or buffer traps[13, 14]. In order to improve the surface state induced partial depletion of 2DEG channel, u-GaN cap layer grown on AlGaN barrier layer has been introduced to the conventional AlGaN/GaN heterostructure[7-11]. It is well known that u-GaN cap layer reduces the surface state densities via surface passivation[15]. The u-GaN cap layer has also been utilized to increase the Schottky barrier height of AlGaN/GaN heterostructures, by which gate leakage current was significantly reduced[16]. Using an appropriate u-GaN cap layer in p-GaN gate HEMTs allows for high drain current and low R_ON. Nevertheless, there is no clear evidence for correlation between the u-GaN cap layer thickness and the AlGaN/GaN interface states. To investigate the interface trap of the AlGaN/GaN heterostructure devices, the conductance dispersion method has been adapted to analyze the interface traps of the multi-layered AlGaN/GaN HEMT[14-17]. Using the conductance dispersion method allows for separating the frequency responses of slow and fast states. The meaning of the slow trap level is attributed to a relatively long carrier lifetime at deep-level interface traps, while the fast trap level is determined by a relatively short carrier lifetime at shallow-level interface traps[9, 17]. It has been explained that the interface traps assist the carrier tunneling[18]. It is assumed that the leakage current characteristics according to the trap level of the u-GaN/AlGaN interface below p-GaN gate and the performance of the power device are closely related[19, 20].

In this paper, to study the effects of varying the u-GaN cap layer thickness, the frequency dependent capacitance and conductance was measured to analyze the interface trap states. The convolution of the shallow and the deep trap states for the thin u-GaN cap layer thickness of below 20-nm was investigated to understand the fast and slow traps at the interface. Furthermore, we investigated the impact of variations in the distribution of shallow and deep defect levels with respect to the thickness of the u-GaN cap layer on the gate leakage current.

The p-type GaN gate HEMTs were fabricated on an AlGaN/GaN heterostructure grown via metal organic chemical vapor deposition (MOCVD) on a Si (111) substrate. The layers were composed of a 200-nm AlN nucleation layer, a 3.5-μm semi-insulating GaN layer, a 200-nm GaN channel, an 8-nm undoped Al_0.22Ga_0.78N barrier layer, an undoped GaN cap layer followed by a 100 nm-thick Mg-doped p-GaN layer. The dislocation density in the GaN layer was observed to 3.0 × 10⁹ cm-2. The sheet carrier concentration and the electron mobility of the 2DEG obtained from Hall measurement were ns(Hall) = 1.03 × 1012 cm​-2 and μe=2040 cm²/V·s, respectively. The concentrations of Mg-doping for p-GaN is 1.5×1019 cm​-3. Three kinds of undoped GaN layers have been introduced to each device. The thicknesses of each u-GaN are 40 nm, 20 nm, and 10 nm, respectively. The gate length and width are 3 μm and 200 μm, respectively. Figure 1 depicts the schematic of the fabricated p-GaN gate AlGaN/GaN heterostructure field-effect transistors (HFETs). For the source and drain contacts, the Ti/Al/Pd/Au stacking layers were deposited and annealed at 850 °C for 1 min in N​2 ambient via rapid thermal annealing (RTA) process. The gate metal (W) was deposited using electron beam evaporation and then patterned with a lift-off process.

Figure 1. (Color online) Schematic diagram and circuit model of the AlGaN/GaN HFET structure including p-GaN/u-GaN cap layer.

The typical transfer curves (Vg–Id and Vg–Ig) for each device under a drain voltage of 0.1 V are measured using the B1500A semiconductor device parameter analyzer, as shown in Fig. 2. The threshold voltage V_th for each device (i.e., u-GaN 40 nm, u-GaN 20 nm and u-GaN 10 nm cap) are respectively 0.68 V, 0.63 V, and 0.62 V, indicating the normally-off operation. At the gate bias of 6 V, shown in Fig. 2, the drain current for the device with u-GaN 20 nm is 1.5 times larger than that of the device with u-GaN 40 nm. Such result can be explained by the increase in 2-dimensional electron gas of AlGaN/GaN interface corresponding to a decrease in u-GaN cap layer thickness. It has been known that the accumulated electron density at AlGaN/GaN interface increases and therefore the mobility can be enhanced. With reducing the thickness of u-GaN cap layer, the drain current becomes seriously diminished due to the high gate leakage current. When a 10 nm thick u-GaN cap layer is introduced, the gate leakage current becomes 4 times larger compared to the case when a 20 nm thick u-GaN is introduced, as shown in Fig. 2. It is assumed that Mg doping on p-GaN might give a strong effect on the AlGaN/GaN interface below u-GaN of 10 nm, which results in the degradation of the device performance. In this result, the gate leakage current of the 40-nm-thick sample has not been improved compared to that of the 20-nm-thick one. As the thickness of the u-GaN capping layer increases, it is presumed that the two-dimensional hole gas (2DHG) generated at the p-GaN/AlGaN interface accumulates. It seems that the 2DHG may play a role in hindering the reduction of gate leakage current in the 40-nm-thick sample[21]. Figure 3 shows the drain current-voltage curves (Vd–Id) for each device under the respective gate voltages of 0.5, 1, 1.5, 2 V. To estimate the interface trap characteristics at the AlGaN/GaN interface, we utilized the conductance dispersion method based on the circuit model shown in Fig. 1. The parallel circuits of Gp and Cp can be extracted from the measurements of Gm and Cm using the following Eq. (1)[15].

Figure 2. (Color online) Id-Vg and Ig-Vg curves of each AlGaN/GaN HFET with different u-GaN cap layer thicknesses(40, 20, and 10 nm). The inset shows the Id-Vg curves near the threshold voltage of each device.

Figure 3. (Color online) Id-Vd curves of the AlGaN/GaN HFET as a function of gate voltage variation for different thicknesses of the u-GaN cap layer: (a) 40 nm, (b) 20 nm, and (c) 10 nm.

By fitting the resulting curves as a function of frequency using the Eq. (2), the interface trap components, τ and Dit for the single state can be extracted[15-17].

The interface trap components for the multiple states can be extracted using Eq. (3)[15-17].

The solid curves in Fig. 4 show the fitted Gm/ω using Eq. (2) or Eq. (3), from which Dit and τ can be extracted.

Figure 4. The conductance Gg/ω as a function of radial frequency at each gate bias voltage and fitted curves for each AlGaN/GaN HFET with different u-GaN cap layer thicknesses ((a) 40 nm, (b) 20 nm, and (c) 10 nm), respectively.

As u-GaN cap layer thickness reduces from 40 nm to 20 nm, the high frequency (>107 Hz) resonance peak of Gm/ω due to the shallow trap state, rises rapidly as can be observed in Fig. 4(a) and Fig. 4(b). On the other hand, as u-GaN cap layer is reduced to 10 nm, the dispersed curve peak varies from low to high frequency region depending on the gate bias voltage, as shown in Fig. 4(c). These results indicate that thin u-GaN layers of less than 20 nm induce not only deep interface traps in AlGaN/GaN but also non-uniform shallow interface traps in u-GaN. Each trap states consist of the “slow trap” and the “fast trap” states, induces kink in drain current-voltage curves[22]. As the trap level at the AlGaN/GaN interface becomes shallower, the defect density in the continuous level increases[23]. On the contrary, as the trap level at the AlGaN/GaN interface becomes deeper, the defect density decreases, leading to a distribution of discontinuous levels. Consequently, these results are attributed to the increased trap-assisted tunneling at the inhomogeneous shallow interface trap states of thin u-GaN cap layer. Therefore, it can be assumed that gate leakage current increases as the thickness of u-GaN cap layer decreases. The interface trap state energy from the conduction band edge, Ec-Eit can be derived from the following equation[15-17].

Assuming the following parameters for the capture cross section of σT∼3.4×10-15 cm² for an undoped-GaN, the average thermal velocity vT=2.6×107 cm²/s, and the effective density of states in the conduction band Nc=2.2×1018 cm-3,Ec-Eit can be obtained[15-17]. As shown in Fig. 5, the shallow trap density of u-GaN 20 nm is lower than that of u-GaN 40 nm. On the other hand, the shallow trap density of the device with u-GaN 10 nm increases on the contrary to that of u-GaN 40 nm. It has been known that a thick cap layer can induce considerable changes of strain in the AlGaN barrier layer[22]. In other words, the thick u-GaN layer can induce the surface strain relaxation in AlGaN barrier layer, which has been known to be the main cause of the decrease of 2DEG in AlGaN/GaN interfaces according to the reduced piezoelectric polarization effects[19]. We assume that the inhomogeneous surface strain leads to a decrease in electron mobility due to electron scattering, resulting in reduced transport current. The increase in stress in the AlGaN barrier layer leads to an increase in elastic energy in this region[21]. If the elastic energy of the AlGaN barrier layer exceeds a critical threshold, the generation of various crystal defects, such as microcracks or misfit dislocations, becomes energetically favorable near the gate edges[23]. On the other hand, the thin u-GaN (less than 10-nm thickness) on AlGaN barrier has more of shallow interface trap states due to the increased inhomogeneous interface states. Therefore, the thin u-GaN causes the trap-assisted tunneling through the shallow interface trap states[24]. The trap assisted tunneling reduces the carrier concentration in the channel and creating a leakage path from the gate to the channel, resulting in an increase in gate leakage current[25]. In conclusion, as the thickness of the u-GaN cap layer over the AlGaN barrier layer decreases below 20-nm, the reduction in drain current is presumed to be influenced by the gate leakage current mediated by the shallow interface trap states. In this study, it can be understood that thin u-GaN cap layer increases the shallow interface traps, which results in the trap assisted tunneling. On the other hand, thick u-GaN cap layer can induce the strain relaxation in AlGaN barrier, which gives rise to the drain current decrease.

Figure 5. Trap density extracted by the conductance method as a function of trap states energy level for each AlGaN/GaN HFET with different u-GaN cap layer thickness.

In summary, we have studied the effect of u-GaN cap layer integrated in p-GaN/u-GaN/AlGaN/GaN heterostructure field-effect transistors concerned with both the gate leakage and the drain currents which strongly depend on u-GaN thickness. From the conductance method, it was confirmed that thin u-GaN thickness of less than 20-nm can induce multi-level interface trap states level to p-GaN gate integrated AlGaN/GaN HFETs. As the u-GaN thickness increases, the drain current decreases, which can be attributed to the decreased 2DEG at the interface of AlGaN/GaN heterostructure. On the other hand, as the u-GaN thickness decreases, the increased shallow trap state due to the inhomogeneous interface can increase the trap assisted gate leakage current.

This research was supported by Sangji University Research Fund, 2023.