Porous silicon exhibits unique electrical properties, such as charge trapping in localized states[1-3]. Graphene is a popular material due to its transparent, flexible, and conductive properties[4-6]. Various functional devices have been developed to take advantage of the unique properties of porous Si and graphene, such as photodetectors and solar cells[7-9]. This study characterized a hysteresis property in the graphene/porous Si heterostructure by controlling the surface porosity of the Si substrate. Metal assisted chemical etching (MaCE) was used to develop a porous surface on a Si substrate, and chemical vapor deposition was used to create a large area of graphene. The graphene was transferred onto the Si substrate with the porous surface, and then the top and bottom electrodes were formed. The current-voltage characteristics of graphene/porous Si heterostructure devices with varying porosity were measured. The hysteresis property was revealed by the hysteresis curve in the device with high porosity.

The graphene/porous Si heterostructure device was developed through several steps (Fig. 1). The two MaCE steps were conducted to prepare the porous Si layer on the Si substrate. First, the Si substrate was immersed in the mixture solution of HF, AgNO₃, and H₂O₂ (1.1:0.3:5) for 10 seconds at room temperature, after which silver particles were generated on the surface of the Si substrate. Second, the prepared Si substrate with silver nanoparticles was transferred to a solution of HF, H₂O₂, and H₂O (5:0.5:50) and was etched at room temperature. Etching times of 20, 30, and 40 seconds were used to control the porosity of the Si surface. The remaining silver nanoparticles in the porous Si surface were then removed for 30 seconds from the HNO₃ solution. The scanning electron microscopy (SEM) images reveal the different porous surfaces of the Si substrate for the etching times of 20 (a), 30 (b), and 40 (c) (Fig. 2). The porous surface with the longest etching time shows smaller and denser nanostructures on the surface.

Figure 1. (Color online) Schematic illustration of the graphene/porous Si heterostructure devices.

Figure 2. Scanning electron microscopy images of porous Si surface with varying etching times of 20 (a), 30 (b), and 40 s (c).

Next, using a wet transfer method, the extended area of graphene with a sheet resistance of 250–400 Ohm/sq prepared by chemical vapor deposition (Graphene Square INC) was transferred to the porous Si surface. The graphene on a copper foil was polymer coated and transferred onto the copper etchant. The polymer/graphene layer on deionized water was transferred to the porous Si and was dried at room temperature for several hours (Fig. 3(a)).

Figure 3. (Color online) (a) Scanning electron microscopy images of representative graphene/porous Si. A darker contrast is observed at graphene/porous Si than that of porous Si. (b) I−V curves of graphene/porous Si devices with varying the second step etching times as 20 (green line), 30 (blue line), and 40 seconds (red line). Also, the I−V curve of graphene/Si was obtained (black line).

To fabricate the device, the top of the graphene/SiO₂/Si area and the backside of the Si substrate were brushed with silver paste to create the top and bottom electrodes, respectively. Once the top electrode created on the graphene/SiO₂ is observed, the electric field can then be applied conformally to the interface of graphene and porous Si.

To investigate the hysteresis properties of graphene/porous Si devices, the I−V characteristic was examined (Fig. 3(b)). The current was measured while the voltage was dual swept from 0 to 10 V. The graphene/porous Si device with the etching time of 40 seconds exhibits a clear hysteresis loop, with the current increasing linearly in the forward sweep direction from 0 to 10 V, and the larger current in the reverse sweep direction from 10 to 0 V. The graphene/porous Si devices with 20 and 30 seconds etching times exhibit a weak hysteresis loop. The graphene/Si device exhibits no hysteresis loop and displays the same current level in the forward and backward sweep directions. The varying current level of each device was observed to have originated from the different graphene areas.

The charge trapping ability of porous Si may be the source of the hysteresis loop[1-3]. During the forward voltage sweep, the charge density is tuned due to the charges introduced into the porous Si through graphene that may be trapped in the numerous localized states in the porous Si. During the backward voltage sweep, the device with greater charge density exhibits a higher current level than it does in the forward sweep direction, thus creating a hysteresis curve.

To confirm the charge trapping in the porous Si, the current was measured under light illumination (Fig. 4). In the dark condition, the I−V curve exhibits the hysteresis curve. However, the hysteresis curve disappeared under the 520 -nm continuous wave laser with a power of 1 mW. The charging effect in the graphene/porous Si device is eliminated by the excitation of the trapped electrons in the localized states of porous Si under light illumination[7,8].

Figure 4. (Color online) The I−V curves of graphene/porous Si device with the etching time of 40 seconds under the dark (black line) and light condition (red line).

This study reveals the hysteresis properties in the graphene/porous Si heterostructure device. The graphene/porous Si device was developed using a porous Si substrate with varying surface porosity, which was controlled by the etching time in the MaCE process. The device with high porosity exhibits a larger window in the hysteresis curve. The I−V curve measurement under light illumination was used to examine this hysteresis property, which may be related to the charge trapping ability of porous Si. In the light condition, the hysteresis curve disappeared due to the excitation of trapped electrons in the porous Si. The graphene/porous Si heterostructure device can be applied in various electronic devices.